| 摘要 |
<p>A NAND flash memory device with a reduced memory cell size is provided to define a control gate of NAND flash cells by a self-aligned spacer. A semiconductor substrate of a first conductivity type is prepared. Low-density junction regions(177) of a second conductivity type are formed in the surface of the semiconductor substrate. A control gate(124) is formed on a stack layer of a thermal oxide layer, a polysilicon layer and a CVD(chemical vapor deposition) insulation layer that are formed on the substrate. Self-aligned spacers are formed on the lateral surface of the thermal oxide layer, the polysilicon layer, the CVD insulation layer and the control gate. The control gate is made of a polysilicon layer, a polycide layer or a combination layer thereof.</p> |
