发明名称 Adjusting methods of arithmetic multiplying circuit, drive circuit, and phase margin
摘要 An arithmetic amplifying circuit for driving a capacitive load is provided including a voltage follower circuit converting an input signal to impedance, and a resistance circuit which is serially connected between the voltage follower circuit and an output of the arithmetic amplifying circuit. The voltage follower circuit includes a differential section, which amplifies a differential between the input signal and the output signal of the voltage follower circuit, and an output section, which outputs the output signal of the voltage follower circuit based on an output of the differential section, and drives a capacitive load via the resistance circuit.
申请公布号 US2007290752(A1) 申请公布日期 2007.12.20
申请号 US20070891844 申请日期 2007.08.13
申请人 MAKI KATSUHIKO 发明人 MAKI KATSUHIKO
分类号 G09G3/36;H03F3/45;G09G3/20;H03K5/02;H03K19/0185;H04N5/66 主分类号 G09G3/36
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