SEMICONDUCTOR MEMORY DEVICE

摘要

A voltage switching circuit used in a row decoder includes: PMOS transistor P 2 and high-voltage NMOS transistor D 3 connected in series between VRDEC and TG; PMOS transistor P 1 and high-voltage NMOS transistor D 2 connected in series between VRDEC and NA; NMOS transistor N 2 and high-voltage NMOS transistor D 6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N 1 and high-voltage NMOS transistor D 5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P 1 and P 2 are cross-coupled. Gates of D 3 and D 2 are coupled to TG and NA, respectively.