| 摘要 |
A memory device including a small clock buffer is provided to achieve low power consumption, by controlling on/off of the small clock buffer. A clock enable buffer(710) outputs an internal clock enable signal by buffering a clock enable signal. A clock enable control part(720) outputs a first signal and a second signal by synchronizing the internal clock enable signal to a small clock signal. A clock control part(730) outputs a clock buffer enable signal and a small clock buffer enable signal by receiving the first and the second signals. A clock buffer(740) outputs a clock pulse by buffering a clock and is driven according to the clock buffer enable signal. A small clock buffer(750) is driven according to the small clock buffer enable signal, and outputs the small clock signal by buffering the clock.
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