Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals

摘要

The invention relates to a circuit arrangement ( 4 ) for a PLL to be used in a terminal ( 50 ) of a time division cellular network. In a PLL according to the invention, the control voltage ( 32 a) to a VCO ( 33 ) in the PLL is kept at a desired value also during time slots in which the terminal is not receiving or transmitting messages. The settling time for a PLL according to the invention is shot and the spurious effects caused by the power up thereof are small. The invention further relates to a method of operation for a PLL.