| 摘要 |
PROBLEM TO BE SOLVED: To provide a high speed dynamic frequency divider which is to be operated in high speed with low power consumption. SOLUTION: The frequency divider includes a buffer 30, a function selector 31, and an inverter 32. An output of the function selector 31 is to be inputted to the buffer 30. An output of the buffer 30 is to be performed feed back to the function selector 31 by two paths. One of the paths includes the inverter, while the other does not include. The function selector 31 is designed to select one path by synchronizing to an input clock CK. The output of the buffer 30 is to be determined by the inverter 32 in a certain timing. In the next timing, the output of the buffer 30 is made to be held to the same value by selecting a path which does not include the inverter 32 by the function selector 31. COPYRIGHT: (C)2008,JPO&INPIT
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