| 摘要 |
A circuit for controlling a data output enable signal is provided to control the data output enable signal by detecting an operation frequency. A detection signal generation part(100) generates an act signal by delaying an active signal for a first time and outputs an end signal by delaying the act signal for a second time, and outputs a DLL(Delay Locked Loop) clock count signal by performing a logic operation of the act signal and a signal obtained by delaying a DLL clock for a third time. A detector(200) outputs a counting signal by counting a rising edge of the DLL clock count signal until the end signal is enabled. A decoder part(300) outputs a selection signal by decoding the counting signal. An output enable signal generation part(400) includes a plurality of shift registers receiving an internal read signal and CAS latency, and outputs an output enable signal by delaying the internal read signal through a shift register selected by the selection signal and the CAS latency.
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