发明名称 Chip stack package utilizing a dummy pattern die between stacked chips for reducing package size
摘要 The chip stack package includes at least a printed circuit board having a bond finger and a ball land, and at least two semiconductor chips stacked on the printed circuit board while being spaced from each other and formed with a plurality of bonding pads. A dummy pattern die is attached to the upper surface of each semiconductor chip. The dummy pattern die is formed with a circuit pattern on its lower surface for electrical connection to the semiconductor chip. The dummy pattern is also formed with a via pattern on its upper side which is connected to the circuit pattern. The first solder balls electrically connects the bond finger with the circuit pattern while electrically connecting the via pattern of stacked dummy pattern dies with the circuit pattern. The second solder balls are attached to the ball land of the printed circuit board.
申请公布号 US2007228579(A1) 申请公布日期 2007.10.04
申请号 US20060485495 申请日期 2006.07.12
申请人 KANG TAE MIN 发明人 KANG TAE MIN
分类号 H01L23/52 主分类号 H01L23/52
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