| 摘要 |
<P>PROBLEM TO BE SOLVED: To facilitate layout design while inhibiting enlargement of a cell size of an SRAM cell. <P>SOLUTION: The SRAM cell CELL 1 has six transistors of a data holder 2 and two transistors of a reader 3. A plurality of SRAM cells are vertically and laterally repetitively formed and arranged in a vertically elongate rectangle, and first layer wiring is used to connect between the transistors. Layers constituting the SRAM cell CELL 1 include five vertical rows of diffusion layers SDG in a laterally elongate rectangle which are separately formed and arranged in parallel. Vertically elongate gates GP are formed and arranged at every half pitch of the lateral size, and contacts of a source or a drain are formed separately at a 1/4 pitch of the lateral size of the gate GP. A high potential power supply Vss wire, a low potential power supply Vss wire, a bit line BL wire, a bit line/BL wire, and a word line WL wire are drawn by wires of second and subsequent layers through a first via provided at a predetermined position in the SRAM cell CELL 1. <P>COPYRIGHT: (C)2007,JPO&INPIT |
