| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital DLL circuit capable of easily cancelling an external gate delay error even in the presence of power supply voltage, temperature or process variations and eliminating the need for occurrence of remaking an LSI after clarification of the presence of a delay error and addition of another delay adjustment mechanism other than a DLL. <P>SOLUTION: The digital DLL circuit includes: a first register 11 for holding a delay designation value for designating a delay; a second register 12 for designating a gate delay correction value inside the LSI; a digital control variable delay circuit 13; a control circuit 15 for generating a delay control value DCV so as to control a delay of the variable delay circuit 13 in a way of being maintained to a delay designation value of the first register 11; and an adder circuit 15 that adds the gate delay correction value GDCV held in the second register 12 to the delay control value DCV outputted from the control circuit 15. <P>COPYRIGHT: (C)2007,JPO&INPIT |
