发明名称 |
Digital signal coding apparatus, digital signal decoding apparatus, digital signal arithmetic coding method and digital signal arithmetic decoding method |
摘要 |
In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.
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申请公布号 |
US2007205927(A1) |
申请公布日期 |
2007.09.06 |
申请号 |
US20070797462 |
申请日期 |
2007.05.03 |
申请人 |
SEKIGUCHI SHUNICHI;YAMADA YOSHIHISA;ASAI KOHTARO |
发明人 |
SEKIGUCHI SHUNICHI;YAMADA YOSHIHISA;ASAI KOHTARO |
分类号 |
H03M7/34;G06T9/00;H03M7/40;H04N7/24;H04N7/26;H04N7/52 |
主分类号 |
H03M7/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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