| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit for pulling data intermittently recorded and whose head includes a synchronization pull-in pattern region at high speed without providing a special VCO with a plurality of phase error outputs. <P>SOLUTION: The PLL circuit includes: an AD converter 4; a phase comparator 5 for calculating a phase error from the output signal of the AD converter 4; a frequency system filter 6; a phase system filter 7; a phase error read means 8 and a phase error conversion means 9 for reading the phase error calculated by the phase comparator 5 in a prescribed timing and producing an output corresponding to the read value; an adder 10 for adding the output of the frequency system filter 6, the output of the phase system filter 7, and the output of the phase error conversion means 9; a DA converter 11; and a VCO 12 for outputting an oscillation output used for the sampling clock of the AD converter 4 on the basis of the output voltage of the DA converter 11. <P>COPYRIGHT: (C)2007,JPO&INPIT |
