发明名称 |
Error-detection flip-flop |
摘要 |
An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
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申请公布号 |
US2007168848(A1) |
申请公布日期 |
2007.07.19 |
申请号 |
US20050323675 |
申请日期 |
2005.12.30 |
申请人 |
TSCHANZ JAMES;MITRA SUBHASISH;DE VIVEK |
发明人 |
TSCHANZ JAMES;MITRA SUBHASISH;DE VIVEK |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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