| 摘要 |
An arithmetic circuit includes a NOR circuit for outputting 1-bit inverted logical OR sf from all of a first bit group x( 6 ) to x( 10 ) containing 0 or more high-order bit of a path metric value composed of a plurality of bits, an inverter for inverting each bit of a second bit group x( 2 ) to x( 5 ) and outputting a third bit group rs( 0 ) to rs( 3 ), an AND circuit for outputting a fourth bit group ns( 0 ) to ns( 3 ) that contain results of calculating a logical AND of sf and rs( 0 ) to rs( 3 ), and a CF output section for outputting a correction factor CF based on ns( 0 ) to ns( 3 ).
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