Memory device with reduced leakage current

摘要

A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal of the pull-down devices. The reduction in leakage current through pull-down devices whenever a read operation is not performed contributes to a significant reduction in overall leakage current in the circuit.