FAST PULL-UP CIRCUIT IN VLSI CIRCUITS

摘要

A fast pull-up circuit in VLSI circuits is provided to reduce pull-up delay time by using a static CMOS circuit as a fast pull-up circuit in order to perform a faster operation in a dynamic-static CMOS logic circuit. In a semiconductor integrated circuit having a dynamic-static logic circuit where a dynamic CMOS and a static CMOS are used in turn, PMOS transistors of a pull-up circuit comprising the static CMOS are connected in parallel. The width of the PMOS transistor is sized as 2P.