SIGNAL PROCESSOR FOR ENDOSCOPE

摘要

PROBLEM TO BE SOLVED: To provide a signal processor for an endoscope using a PLL (Phase Lock Loop)circuit capable of performing frequency acquisition in a simple constitution with it set to a low phase noise characteristic condition.

SOLUTION: The input of a reference clock R-CLK from a CCD driving circuit 17 via a CCD 15 to the PLL circuit 27 is opened/closed by an R-gate 26. A start timing of an intermittent operation control signal (EN) enabling the operation of a phase comparator 28 in a phase adjustment period for reading empty pixels of the CCD 15 is adjusted to synchronize with a variable clock V-CLK by delaying the variable clock V-CLK by a delay circuit 34 and impressed to the phase comparator 28 via a latch circuit 33. The frequency acquisition is thus performed in the simple constitution by changing the R-gate 26 from the close state to the open state with its set to the low phase noise characteristic condition.

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