| 摘要 |
<P>PROBLEM TO BE SOLVED: To restrict erroneous code determination without raising the frequency of a count pulse. <P>SOLUTION: A count pulse generating part 21 generates the count pulse Cp having a pulse width being sufficiently shorter than that of one bit section in a bit string constituting a synch field SF. A bit length counting part 23 counts the number of the count pulses Cp generated from the start bit of the synch field SF to the stop bit. Then, a bit length determining part 30 determines one bit length of one bit section, based on a quotient Q, which is obtained by dividing the number of the count pulses Cp counted by the bit length counting part 23 by the bit number 2<SP>n</SP>of the bit string, and its residue S. A synchronous clock generating part 27 generates a synchronous clock SynCLK at a prescribed timing corresponding to one bit length which is determined by the bit length determining part 30. <P>COPYRIGHT: (C)2007,JPO&INPIT |
