| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor system in which the usability and performance of intra-chip heterogeneous multiprocessor can be improved. SOLUTION: The processor system has a processor and a memory. The processor 1 comprises a control unit 10 for reading a program, a plurality of arithmetic units 20, 30, 40 for transmitting a SIMD instruction in the program read with the control unit, and a shared cache 50 in which the control unit can store the program read from the memory and which the control unit and the plurality of arithmetic units can read data from and write data into. An instruction transmitted by the control unit to the plurality of arithmetic units, in a process that the plurality of arithmetic units execute the instruction, designates whether or not to interrupt the execution of the instruction until reception of an external signal from the arithmetic unit different from the arithmetic unit executing the instruction. COPYRIGHT: (C)2007,JPO&INPIT
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