发明名称 DEAD TIME COMPENSATION ARRANGEMENT OF INVERTOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a dead time compensation device for an inverter capable of preventing a phase current from becoming zero by generating imbalance in a current command to the inverter, preventing the current command to the inverter from becoming zero at the same time, and accurately operating the dead time compensation by shortening a period for passing zero. <P>SOLUTION: The current commands Id<SP>*</SP>, Iq<SP>*</SP>are input in a current command generator 21 of a PM motor having a multi-layer winding, and the current command generator 21 generates the current commands Id_a<SP>*</SP>, Iq_a<SP>*</SP>and Id_b<SP>*</SP>, Iq_b<SP>*</SP>to the respective inverters INVa, INVb. The generated current commands Id_a<SP>*</SP>-Iq_b<SP>*</SP>are input in current control units 12da-12qb through deviation parts 22-25. For the current control units 12da-12qb, voltage commands of a dq axis is sent to the output, and the voltage command is input in coordinate converters 13a, 13b. The coordinate converters 13a, 13b convert the coordinate of the input voltage command into AC voltage elements corresponding to UVW phases of a 3 phases PM motor 30 to output. Error components of the dead time are added to the output voltage components by the dead time compensation value adding parts 19a, 19b, and the added result is input in PWM modulation parts 14a, 14b to perform PWM modulation. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007143320(A) 申请公布日期 2007.06.07
申请号 JP20050335107 申请日期 2005.11.21
申请人 MEIDENSHA CORP 发明人 YAMAMOTO YASUHIRO
分类号 H02M7/537;H02M7/48;H02P21/00;H02P27/04 主分类号 H02M7/537
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