发明名称 SERIAL COMMUNICATION SYSTEM FOR A/D CONVERTER
摘要 <p>PURPOSE:To avoid reception of the undesired A/D conversion data by sending the permitting and inhibiting instructions to an A/D converter from a processor for the A/D conversion. CONSTITUTION:The permission/inhibition of the A/D conversion is controlled at the level of a terminal A of a processor 2. The level of the terminal A is switched between H (high) and L (low) levels by a program of the processor 2. Thus the terminal A is set at an L level (output of a permitting instruction) right before transmission of the request channel data and then at an H level (output of an inhibiting instruction) right after reception of the A/D conversion data respectively. Thus no A/D conversion is carried out even though the noise is put on the line of a request channel with the terminal A set at an H level and turned into a start signal since an A/D converter 1 is not activated. Then it is possible to prevent such a harmful process where the data are broken in a RAM 21 after the undesired A/D conversion data is received by the processor 2.</p>
申请公布号 JPH01177121(A) 申请公布日期 1989.07.13
申请号 JP19880001563 申请日期 1988.01.07
申请人 FUJITSU TEN LTD 发明人 HIGASHIDA HIROBUMI
分类号 G06F3/05;H03M1/12 主分类号 G06F3/05
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