| 摘要 |
A memory circuit includes a plurality of storage cells ( 100 ) arranged in rows and columns thus forming a storage matrix. The storage cells ( 100 ) corresponding to the same bit line ( 21 - 23 ) are divided into several groups ( 60 - 61 ) of cells for the same column, these groups having their own biasing circuit ( 200 ) in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.
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