Vertical-gate mos transistor for high voltage applications with variable gate oxide thickness

摘要

A vertical-gate MOS transistor ( 100 ) is proposed. The vertical-gate MOS transistor is integrated in a semiconductor chip ( 120 ) of a first conductivity type having a main surface, and includes an insulated trench gate ( 110 ) extending into the semiconductor chip from the main surface to a gate depth ( d1 ), said trench gate including a control gate ( G ) and an insulation layer ( 180 ) for insulating the control gate from the semiconductor chip, a source region and a drain region of a second conductivity type formed in the semiconductor chip, at least one of the source region and drain region being adjacent to the insulation layer and extending into the semiconductor chip from the main surface to a region depth ( d2 ) lower than the gate depth, wherein the insulation layer includes an external portion ( 180a ), extending into the semiconductor chip from the main surface to a protection depth ( d4 ) lower than the gate depth, and a remaining internal portion ( 180b ), the external portion having an external thickness ( d5 ) and the internal portion having an internal thickness ( d6 ) lower than the external thickness.