发明名称 Testing method and testing apparatus
摘要 A testing method of a semiconductor integrated circuit device includes a testing step of conducting a functional test by supplying test pattern data to a semiconductor integrated circuit device mounted upon a testing apparatus, and a post processing step conducted after the testing step for continuously driving the semiconductor integrated circuit device by supplying dummy test pattern to the semiconductor integrated circuit device, wherein the test pattern data is supplied with a first system clock speed while the dummy test pattern data is supplied with a second, slower system clock speed, the post processing step switching a system clock speed of the testing apparatus from the first system clock speed to the second system clock speed at the same time as finishing of the testing step.
申请公布号 US2007091698(A1) 申请公布日期 2007.04.26
申请号 US20060334399 申请日期 2006.01.19
申请人 FUJITSU LIMITED 发明人 WATANABE TAKAO;ISHIHARA SHIGENOBU
分类号 G11C29/00 主分类号 G11C29/00
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