发明名称 |
Fault-tolerant multi-core microprocessing |
摘要 |
One embodiment disclosed relates to a method of executing program code on a target microprocessor with multiple CPU cores thereon. One of the CPU cores is selected for testing, and inter-core context switching is performed. Parallel execution occurs of diagnostic code on the selected CPU core and the program code on remaining CPU cores. Another embodiment disclosed relates to a microprocessor having a plurality of CPU cores integrated on the microprocessor chip. Inter-core communications circuitry is coupled to each of the CPU cores and configured to perform context switching between the CPU cores.
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申请公布号 |
US7206966(B2) |
申请公布日期 |
2007.04.17 |
申请号 |
US20030690727 |
申请日期 |
2003.10.22 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
BARR ANDREW HARVEY;POMARANSKI KEN GARY;SHIDLA DALE JOHN |
分类号 |
G06F11/00;G06F15/167;G06F11/22;G06F11/27 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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