发明名称 LOGIC VERIFICATION DEVICE AND METHOD FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a system dynamically changing a configuration of a test bench for efficiently verifying a data path when a test description for individual verification of each processing block is used for system verification in the data path made by combining a plurality of processing blocks in data path verification. SOLUTION: In this integrated circuit verification method, a common sequence basic class including a function for arranging a path model for input/output operation is defined, and a sequence class conforming thereto is defined for each processing block. In the test description, using a data path common verification function including a function for executing the path model arrangement function, the model arrangement function for each processing block is operated, and the test bench is configured. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007087175(A) 申请公布日期 2007.04.05
申请号 JP20050276132 申请日期 2005.09.22
申请人 CANON INC 发明人 YAMAZAKI TATSUHIKO;YUASA NOBUYUKI
分类号 G06F17/50 主分类号 G06F17/50
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