发明名称 |
Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals |
摘要 |
Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.
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申请公布号 |
US7199634(B2) |
申请公布日期 |
2007.04.03 |
申请号 |
US20040005821 |
申请日期 |
2004.12.07 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHO GEUN-HEE;KIM KYU-HYOUN |
分类号 |
H03K3/017;G11C8/00;H03K5/04;H03K5/135;H03K5/151;H03K5/156;H03L7/081 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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