发明名称 Delay locked loop for high speed semiconductor memory device
摘要 A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.
申请公布号 US2007069782(A1) 申请公布日期 2007.03.29
申请号 US20060528633 申请日期 2006.09.28
申请人 HYNIX SEMICONDUCTOR INC 发明人 SHIN BEOM-JU
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
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