| 摘要 |
<p>A method for manufacturing a nonvolatile memory apparatus is provided to facilitate deposition of a dielectric and a control gate electrode layer by expanding an interval between floating gate electrodes, and an inner width thereof. An isolation layer(108) is formed on a substrate(100) to define an active region(104) and a field region on the substrate. A tunnel oxide layer(112) is formed on a surface of the substrate of the active region. A sacrificial layer pattern(120) having an opening unit is formed. The opening unit exposes the tunnel oxide layer and the substrate of the field region. A conductive layer(124) is successively formed on a surface of the tunnel oxide layer, a sidewall of the opening unit, and a surface of the sacrificial layer pattern. The opening unit where the conductive layer is formed is fully gap-filled to form a gap-fill layer(128) consisting of an HDP-CVD oxide layer, USG, BPSG, or SOG. The conductive layer and the gap-fill layer are planarized when the surface of the sacrificial layer pattern is exposed to form a preliminary conductive layer pattern. The preliminary conductive layer pattern is connected to both edges of the first conductive layer pattern in a body and has a second conductive layer pattern extended to a vertical direction. The sacrificial layer pattern and the part of the planarized gap-fill layer are firstly etched to expose the second conductive layer pattern of the preliminary conductive layer pattern. The part of the second conductive layer pattern of the exposed preliminary conductive layer pattern is secondly etched by using the first etched sacrificial layer pattern and the gap-fill layer as etching masks. The first etched gap-fill layer is removed and a part of the first etched sacrificial layer pattern is thirdly etched. The third etched sacrificial layer pattern is removed at the same time the part of the first conductive pattern of the second etched preliminary conductive layer pattern is fourthly etched to form a completed conductive pattern.</p> |
