| 摘要 |
PROBLEM TO BE SOLVED: To provide a signal processing circuit capable of achieving speedy data outputitng by immediately outputting reception data regardless of time information added to a reception packet. SOLUTION: Data TS of a time stamp added to a received packet are compared with a cycle time CT of an internal cycle counter and when the cycle time CT is greater than the time stamp data TS, reception data stored in a FIFO 110 are outputted to an application side. In addition, a flag of time stamp disable is set from a CPU 30 to a CFR 111, and the reception data received and stored in the FIFO are immediately outputted to an application side regardless of a value of the time stamp. COPYRIGHT: (C)2007,JPO&INPIT |
