| 摘要 |
Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.
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