| 摘要 |
The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.
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