发明名称 |
Dual-gate dynamic logic circuit with pre-charge keeper |
摘要 |
A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.
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申请公布号 |
US2007040584(A1) |
申请公布日期 |
2007.02.22 |
申请号 |
US20050204401 |
申请日期 |
2005.08.16 |
申请人 |
NGO HUNG C;CHUANG CHING-TE;KIM KEUNWOO;KUANG JENTE B;NOWKA KEVIN J |
发明人 |
NGO HUNG C.;CHUANG CHING-TE;KIM KEUNWOO;KUANG JENTE B.;NOWKA KEVIN J. |
分类号 |
H03K19/096 |
主分类号 |
H03K19/096 |
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