| 摘要 |
When reading out flash ROM data from an external interface circuit, a clock for a CPU is stopped only in a period during which the flash ROM is read out and fetch data at the CPU side are held in a fetch bus interface; thereafter, an address of the data that are desired to be read out for the flash ROM is output and the data are taken in. When rewriting into the flash ROM, a fetch target from the CPU is switched to a tuning RAM that stores a copy of the data for a rewrite region, and during that period, data rewrite of the flash ROM is carried out. Reading and writing of the flash ROM data from outside is made possible while the CPU is kept in operation.
|
