| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a test circuit which precisely analyzes signal delay of an input/output circuit, and also to provide its test method. SOLUTION: The test circuit has a cascade form which indicates that an internal output node in a plurality of input/output circuits is connected to an internal output node of another input/output circuit. A pulse input terminal is connected to the internal input node of the input/output circuit at the first stage, and a signal of the pulse input terminal and a signal of the internal output node of the input/output circuit at the final stage are transmitted to a pulse output terminal through a logic circuit. The logic circuit forms a pulse signal having a pulse width which indicates that the variation timing of the pulse input terminal is synchronized with the variation timing of the signal of the internal output node of the input/output circuit at the final stage. COPYRIGHT: (C)2007,JPO&INPIT
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