| 摘要 |
<p>The operation-dependent power consumption (AC component) and the noise generated from a clock distributing circuit itself are reduced in distributing a clock, and the skew attributed to the clock distribution is reduced. A clock distributing circuit (20) for distributing a clock to timing generators (10-1 to 10-n) has a clock main path (21) connected to a main path buffer (24) and a clock return path (26) connected to a return path buffer (27). The load capacity of the main path buffer (24) is equal to that of the return path buffer (27). The biases of the buffers are the same potential and are generated by a delay locked-loop circuit (30). The propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of the clock period.</p> |
