| 摘要 |
An apparatus comprising an analog-to-digital converter, a compensation circuit, a partial response equalizer and a non-adaptive Viterbi decoder. The analog-to-digital converter may be configured to convert an input analog signal into a digital signal. The compensation circuit may be configured to generate an output signal by clipping the digital signal. The partial response equalizer circuit may be configured to shape the output signal into a pre-defined target with a delay operator. The decoder may be configured to calculate a minimum error between data in the output signal and other possible data sequences.
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