发明名称 METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING
摘要 A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
申请公布号 US2006270071(A1) 申请公布日期 2006.11.30
申请号 US20060379380 申请日期 2006.04.20
申请人 发明人 CHANG HSIEN-CHANG;HOU CHIA-HSIN;CHU TSU-YU;CHEN KO-TING
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
主权项
地址