发明名称 QUALIFYING SYSTEM AND METHOD FOR LOGIC CELL LIBRARY
摘要 A logic cell library verifying system and method are provided to perform a library verifying process on various logic cell libraries quickly and exactly by using a form converter. A logic cell library verifying system comprises a form converter(110) for converting the form of each library to an aiming form adequate for each verifying unit, a sample generator(120) for generating a verifying cell sample using each cell of the converted library, a cell comparator(130) for comparing a new library with a conventional library through one-to-one cell comparison, a function verifying unit(140) for checking an output value corresponding to an input value, a processing rate verifying unit(150) for measuring an internal turnaround time from input to output, a power consumption verifying unit(160) for measuring a power value consumed in a cell treating process of each library, a correlation verifying unit(170) for checking physical design information corresponding to logical design information of each library.
申请公布号 KR100650866(B1) 申请公布日期 2006.11.21
申请号 KR20050130780 申请日期 2005.12.27
申请人 DONGBU ELECTRONICS CO., LTD. 发明人 JEON, YONG CHUL;LEE, SUNG YOUN
分类号 H01L21/00 主分类号 H01L21/00
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