| 摘要 |
A clock recovery circuit for establishing bit synchronization with a received signal. The clock recovery circuit comprises a conventional early-late gate circuit and a loop filter. The loop filter receives an output signal of an early sample circuit included in the early-late gate circuit and an output signal of a late sample circuit included in the early-late gate circuit to generate a control signal output. The control signal is input to a clock-producing device included in the early-late gate circuit. The clock-producing device generates a clock at an ideal impulse-producing time controlled by the control signal. The ideal impulse-producing time is a middle point of the n-th symbol of the received signal.
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