NON-VOLATILE FERROELECTRIC MEMORY DEVICE WITH CIRCUIT FOR CORRECTING FAIL CELL

摘要

A nonvolatile ferroelectric memory device including a defective cell correction circuit is provided to store the horizontal and vertical parity of a main memory cell array in an additional horizontal/vertical parity check cell array, and to correct an error code with a fail by comparing code data stored in the horizontal/vertical parity check cell array with sensing data of the main memory cell array. A main memory cell array comprises mÎn main bit lines connected to a nonvolatile ferroelectric memory, and is mapped into m main cell array groups. A horizontal parity check array checks the horizontal parity of the main cell array group and then stores in m horizontal parity arrays. A vertical parity check cell array checks the vertical parity of each main cell array group and then stores in n vertical parity arrays. An error correction code processing part(80) corrects error data generated in a corresponding column into normal data by comparing data of the main memory cell array with code data stored in the horizontal parity check cell array and code data stored in the vertical parity check cell array.