A radio (10) executes a method (100) for entering and exiting a halt status. Radio (10) has a control unit (18) and an internal timing unit (16). The timing unit (16) has execution logic (32), a status register (46) a counter (30) and a clock source (37). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the execution logic (32). One of these instructions is a 'SWITCH CLOCK' instruction causing the timing unit (16) to switch between clock signals. One of the instructions is 'HALT COUNTER' causing the radio (10) to enter a halt state. The radio (10) can be synchronized to the end of a first communication frame received by it after exiting a halt state. <IMAGE>
申请公布号
EP0952675(B1)
申请公布日期
2006.10.18
申请号
EP19980107473
申请日期
1998.04.24
申请人
FREESCALE SEMICONDUCTOR, INC.
发明人
NORMAN, ODED;REFAELI, MOSHE;PERLMAN, BOAZ;SALANT, YORAM;MCALINDEN, PAUL