发明名称 |
P-channel charge trapping memory device with sub-gate |
摘要 |
A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first inversion region, a second inversion region, and a channel region between the first inversion region and the second inversion region. The semiconductor device further includes a control gate over the channel region and at least one sub-gate over the first and second inversion regions, wherein the control gate does not extend over the at least one sub-gate.
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申请公布号 |
US2006226467(A1) |
申请公布日期 |
2006.10.12 |
申请号 |
US20050100518 |
申请日期 |
2005.04.07 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
LUE HANG-TING;WU MIN-TA;LAI ERH-KUN;SHIH YEN-HAO;HO CHIA-HUA;HSIEH KUANG-YEU |
分类号 |
H01L29/788 |
主分类号 |
H01L29/788 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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