发明名称 Integrated circuit test mode securisation
摘要 <p>The circuit has a logic circuit (2), and storage cells (3) connected to the circuit (2). A connection control module (4) connects the cells, according to a predetermined order, to form a test circuit, when the module`s input (41) receives a valid identification key and the cells receive a test reading or writing control signal. The module connects the cells to form a diversion circuit when the input does not receive the key. - An INDEPENDENT CLAIM is also included for a chip card including an electronic circuit.</p>
申请公布号 EP1560031(B1) 申请公布日期 2006.08.30
申请号 EP20040293096 申请日期 2004.12.22
申请人 STMICROELECTRONICS S.A. 发明人 BANCEL, FREDERIC;HELY, DAVID
分类号 G01R31/3185;G01R31/317;G06F12/14;G06F21/79 主分类号 G01R31/3185
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