发明名称 Virtual ground circuit for reducing SRAM standby power
摘要 A method of operating a memory circuit having a plurality of blocks of memory cells ( 400-404 ) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells ( 400 ) is selected in response to a first address signal (RA<SUB>Y0</SUB>). A row of memory cells ( 430-436 ) in the first block of memory cells is selected in response to a second address signal (RA<SUB>X0</SUB>). A first voltage is applied to a first power supply terminal ( 412 ) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal ( 412 ) of another block of memory cells ( 402 ) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.
申请公布号 US7099230(B1) 申请公布日期 2006.08.29
申请号 US20050106896 申请日期 2005.04.15
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 TRAN HIEP V.
分类号 G11C8/00 主分类号 G11C8/00
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