发明名称 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
摘要 The present invention provides, in one embodiment, a method of fabricating a semiconductor device ( 100 ). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128 , implanting a first dopant through the oxide layer 120 , into the substrate 104 in the first dopant region 122 , and adjacent a gate structure 114 , and substantially removing the oxide layer 120 from the substrate within the second dopant region 128 . Subsequent to the removal of the oxide layer 120 in the second dopant region 128 , a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
申请公布号 US7098099(B1) 申请公布日期 2006.08.29
申请号 US20050064583 申请日期 2005.02.24
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 HORNUNG BRIAN E.;YOON JONG;RILEY DEBORAH J.;CHATTERJEE AMITAVA
分类号 H01L21/8238 主分类号 H01L21/8238
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