发明名称 GATE BIAS CIRCUIT MOS CHARGE COUPLED DEVICES
摘要 A biasing circuit for use with a Charged Coupled Device (CCD) that creates a gate bias voltage by maintaining a model or surrogate representation of the surface potentials within the CCD storage and barrier regions. In one embodiment the invention is a bias circuit that includes at least a first and second model transistor for modeling the two regions. The first model transistor is connected to a supply voltage to provide a first reference voltage at a first node, and models the first charge storage region. A resistive circuit element is coupled between the first node N1 and a second node N2 in order to allow a step voltage to be developed. The second model transistor is in turn connected to the second node N2 and provides the bias voltage at an output portion that can be used to control the gate of the barrier region. The model circuit therefore allows a proper bias voltage to be maintained through process and operating condition variations.
申请公布号 WO2006009895(A3) 申请公布日期 2006.08.10
申请号 WO2005US21566 申请日期 2005.06.17
申请人 KENET, INC.;ANTHONY, MICHAEL, P.;VENUTI, JEFF 发明人 ANTHONY, MICHAEL, P.;VENUTI, JEFF
分类号 H01L29/732;H01L27/148 主分类号 H01L29/732
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