FLOOR PLAN METHOD AND COMPUTING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To speedily design a floor plan considering delay and layout in large-scale and high performance LSI circuit design in recent years. SOLUTION: A delay estimated value of an inter-bloc network is calculated, and a maximum wiring length keeping the delay estimated value of the inter-block network is obtained from the estimated value and the delay character of inter-block network rule to set an evaluation function reflecting the delay character of each inter-bloc network rule and the maximum wiring length. The floor plan is carried out automatically using the evaluation function. COPYRIGHT: (C)2006,JPO&NCIPI