| 摘要 |
PROBLEM TO BE SOLVED: To provide a comparator that can be made small in area and moreover, that is very high in calculation speed, when being configured as an integrated circuit. SOLUTION: The comparator comprises first and second delay circuits for commonly inputting a clock signal to each of input terminals; a first latch circuit including a first logic gate for inputting the output signal of the first delay circuit to a first input terminal, and a second logic gate for inputting the output signal of the second delay circuit to a first input terminal; and a second latch circuit for latching a signal outputted from the output terminal of the first logic gate and a signal outputted from the output terminal of the second logic gate. The delay time of the first delay circuit is a variable delay time controlled by a first digital signal inputted from the outside, and the delay time of the second delay circuit is a variable delay time, controlled by a second digital signal inputted from the outside. COPYRIGHT: (C)2006,JPO&NCIPI
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