| 摘要 |
<p>A transistor circuit for an array device comprises a plurality of thin film transistors electrically connected in parallel and provided on a common substrate. The transistors are arranged on the substrate as at least two rows (20<SUB>i</SUB>, 2O<SUB>2</SUB>, 2O<SUB>3</SUB>) of transistors, and the source lines (30) of the transistors in the first and second rows have different widths and the drain lines (32) of the transistors in the first and second rows have different widths. All sources (30) are connected together and all drains (32) are connected together, and a source connection is provided to an end portion of the wider source lines and a drain connection is provided to an end portion of the wider drain lines. This provide a source and drain layout that reduces layout area and pitch of wide channel TFTs, whilst preventing degradation in the source and drain terminals/lines due to high current densities. The layout essentially comprises groups of small parallel TFTs, which are in turn connected in parallel.</p> |
